Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array that includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks of 64 pages of single level cells (SLC) or 128 pages of multilevel cells (MLC), where each page is typically 2048 bytes of data on 32 word lines. Each of the cells within a block can be electrically programmed on a random basis by charging the floating gate.
The data in a cell is determined by the presence or absence of charge on the floating gate. Each memory cell can be programmed as an SLC or MLC. Each cell's threshold voltage (Vt) determines the data that is stored in the cell. For example, in an SLC, a Vt of 0.5V can indicate a programmed cell while a Vt of −0.5V might indicate an erased cell. The multilevel cell has multiple Vt ranges that each indicates a different state. Multilevel cells can take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage distribution for the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell. The charge can be removed from the floating gate by a block erase operation.
FIG. 1 illustrates a typical prior art Vt distribution diagram where the vertical axis is the quantity of cells and the horizontal axis is the threshold voltage Vt. The most negative state 101 is typically referred to as the erased state, has a negative voltage, and is typically represented as a logical “11”. The programmed states are typically referred to as logical “01” 102, logical “00” 103, and logical “10” 104 states and are programmed from the erased state 101.
The variations in each Vt distribution width 110 is an important parameter to control during programming. The tightest possible distribution is desired, as shown in FIG. 1, in order to produce greater spacing 115 between each of the states 101-104. This enables easier discrimination between states 101-104 since the possibility of a higher voltage of one distribution overlapping a lower Vt of the next distribution is reduced.
As illustrated in FIG. 2, conventional SLC and MLC programming use incrementally increasing (e.g., ΔV) programming pulses 200 that are applied to the access lines (e.g., word lines) of the memory cell array to achieve discrete levels of Vt for the cells in the array. Between each program pulse, a verify is performed to determine if the cell's target Vt has been achieved. Memory cells that have reached their target Vt are inhibited from further programming during subsequent pulses by biasing of the data line (e.g., bit line).
FIG. 2 shows an initial erased distribution 201 that is moved to a more positive, programmed state by the application of the programming pulses 200 to control gates of the memory cells. The programming pulses start at Vstart and increment by a step voltage ΔV from the previous pulse. After the first programming pulse, the distribution 202 has moved towards the 0V origin. The third programming pulse has slightly tightened the distribution 203 as well as moved it in a positive direction. The fourth programming pulse has moved and tightened the distribution 204 even further.
It can be seen from FIG. 2 that the width of the distribution is driven by the programming pulse step voltage. If the step voltage is reduced, the final distribution width is reduced. However, there is a point at which reducing the step voltage has no further affect on the distribution width. At this point, a “saturation” of the distribution width has been reached. This saturation area can be different for each memory cell. Thus, even if the program step voltage is ΔV, the final distribution width might be greater than ΔV.
An additional problem with reducing the programming step voltage is the affect on programming throughput. As the step voltage is reduced, the amount of time required to program a memory cell is increased.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce Vt distribution width without significantly impacting the programming throughput of the memory device.